mitsubishi semiconductor PS11032 flat-base type insulated type jan. 2000 PS11032 integrated functions and features ? converter bridge for 3 phase ac-to-dc power conversion. ? 3 phase igbt inverter bridge configured by the latest 3rd. generation igbt and diode technology. ? inverter output current capability i o (note 1): type name,lotno. 30 29 28 27 26 25 24 23 22 21 60 4.5 9 25 63 ? (69) 36 45.72 2 4 5.08 0.4 0.6 1.2 0.6 74 ? 50.7 ?.8 15 3.5 3 ?.5 16.5 ?.5 8.5 ?.5 16.5 ?.5 25 ?.5 (25.7) 22 55.5 4 440 4-r3 2-r4.5 2-r2.25 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 terminals assignment : 1. cbu+ 2. cbu? 3. cbv + 4. cbv 5. cbw+ 6. cbw 7. vd 8. up 9. vp 10. wp 11. un 12. vn 13. wn 14. fo 15. vamp 16. gnd 21. p1 22. r 23. s 24. t 25. n1 26. p2 27. u 28. v 29. w 30. n2 application acoustic noise-less 0.2kw/200v ac class 3 phase inverters, motor control applications, and motors with built-in small size inverter package package outlines mitsubishi semiconductor PS11032 flat-base type insulated type integrated drive, protection and system control functions: ? p-side igbts : drive circuit, high-level-shift circuit, bootstrap circuit supply scheme for single control-power-source drive, and un- der voltage (uv) protection. ? n-side igbts : drive circuit, dc-link current sense and amplifier circuits for overcurrent protection, control-supply under-voltage protection (uv), and fault output (f o ) signaling circuit. ? fault output : n-side igbt short circuit (sc), over-current (oc), and control supply under-voltage (uv). ? inverter analog current sense : n-side igbt dc-link current sense. ? input interface : 5v cmos/ttl compatible, schmitt trigger input, and arm-shoot-through interlock protective function. type name PS11032 i o (100%) 1.5arms i o (150%; 60sec) 2.25arms motor rating 0.2 kw/200v ac (note 1) : the inverter output current is assumed to be sinu- soidal and the peak current value of each of the above loading cases is defined as : i op = i o ? ` 2, t c < 100c (fig. 1)
mitsubishi semiconductor PS11032 flat-base type insulated type jan. 2000 w v n2 t s r p1 p2 u vd up vp wp un vn wn fo v(amp) gnd input signal conditioning (interlock circuit) level shifter drive circuit drive circuit uv protection + uv protection fo circuit oc/sc protection n1 internal functions block diagram condition symbol item ratings unit applied between p2-n2 applied between p2-n2, surge-value applied between p2-u.v.w, u.v.w-n2 applied between p2-u.v.w, u.v.w-n2 t c = 25c, ( ) means i c peak value v cc v cc(surge) v p or v n v p(s) or v n(s) ic(icp) supply voltage supply voltage (surge) each output igbt collector-emitter static voltage each output igbt collector-emitter switching voltage each output igbt collector current 450 500 600 600 4 (8) v v v v a maximum ratings (tj = 25c) inverter part condition symbol item ratings unit 3 f rectifying circuit 1 cycle at 60hz, peak value non-repetitive value for one cycle of surge current v rrm ea i o i fsm i 2 t repetitive peak reverse voltage recommended ac input voltage dc output current surge (non-repetitive) forward current i 2 t for fusing 800 220 10 100 42 v vrms a a a 2 s converter part symbol item ratings unit v d , v db v cin v fo i fo i amp supply voltage input signal voltage fault output supply voltage fault output current dc-link igbt current signal amp output current C0.5 ~ 20 C0.5 ~ +7.5 C0.5 ~ +7.5 15 1 v v v ma ma control part (fig. 2)
mitsubishi semiconductor PS11032 flat-base type insulated type jan. 2000 condition symbol item ratings unit (note 2) (fig. 3) 60 hz sinusoidal ac applied between all terminals and the base plate for 1 minute. mounting screw: m4 t j t stg t c v iso junction temperature storage temperature module case operating temperature isolation voltage mounting torque C20 ~ +125 C40 ~ +125 C20 ~ +100 2500 0.98 ~ 1.47 c c c vrms nm total system (note 2) : the indicated values are specified considering the safe operation of all the parts within the asipm. the max. ratings for the asipm power chips (igbt & fwdi) is tj < 150. condition symbol item ratings inverter igbt (1/6) inverter fwdi (1/6) converter di (1/6) case to fin thermal, grease applied (1 module) rth(jc) q rth(jc) f rth(jc) fr rth(cf) junction to case thermal resistance contact thermal resistance min. c/w c/w c/w c/w thermal resistance typ. max. 6.1 6.1 4.8 0.074 unit short circuit endurance (output, arm, and load short circuit modes) switching soa tj = 25c, input = on, ic = 4a, v d = v db = 15v (shunt voltage drop not included) tj = 25c, Ci c = 4a tj = 25c, i fr = 5a v r = v rrm , tj = 125c 1/2 bridge inductive, input = 5v ? 0v v cc = 300v, i c = 4a, tj = 125c v d = 15v, v db = 15v note: ton, toff include delay time of the internal control circuit. condition symbol item ratings min. v v v ma m s m s m s m s m s typ. max. 0.3 0.6 0.43 1.6 0.5 0.12 2.9 2.9 1.5 8 1.5 0.8 2.5 1.2 ? no destruction ? f o output by protection operation ? no destruction ? no protecting operation ? no f o output electrical characteristics (tj = 25c, v d = 15v, v db = 15v unless otherwise noted) collector-emitter saturation voltage fwdi forward voltage converter diode voltage converter diode reverse current switching times fwdi reverse recovery time v ce(sat) v ec v fr i rrm ton tc(on) toff tc(off) trr (fig. 3) t c case temperature measurement point @v cc 400v, input = 5v ? 0v (one-shot) C20c tj (start) 125c, 13.5v v d = v db 16.5v @v cc 400v, input = 5v ? 0v, tj 125c i c < oc trip level, 13.5v v d = v db 16.5v units
mitsubishi semiconductor PS11032 flat-base type insulated type jan. 2000 v v v v/ m s v v m s c khz m s 400 16.5 16.5 +1 0.8 5.0 100 15 13.5 13.5 C1 0 4.0 2.2 1 applied across p2-n2 terminals applied between v d -gnd applied between cbu+ & cbuC, cbv+ & cbvC, cbw+ & cbwC applied between up ? vp ? wp ? un ? vn ? wn and gnd relates to corresponding inputs t c 100c, tj 125c tj = 25c, v d = 15v, vin = 5v tj = 25c, v d = v db = 15v, vin = 5v applied between input terminal-inside power supply t c 100c, tj 125c relates to corresponding inputs t c = C20c ~ +100c (note 3) relates to corresponding input (fig. 6) i c = i op(100%) v d = 15v i c = i op(200%) tj = 25c (fig. 4) i c = i op(250%) v d = 15v i c = 0a (fig. 4) tj = 25c (fig. 5) tj = 25c (fig. 5) tj = 25c (fig. 5) tj = 25c (fig. 5) t c = tj = 25c (fig. 5) tj = 25c (note 4) open collector output (note 4) circuit current (average) circuit current (average) input on threshold voltage input off threshold voltage input pull-up resistor pwm input frequency arm shoot-through blocking time input interlock sensing inverter dc-link igbt current sense voltage output signal inverter dc-link igbt current sense voltage output limit over current trip level over current delay time short circuit trip level short circuit delay time trip level reset level trip level reset level delay time fault output pulse width fault output current condition symbol item ratings i d i db v th(on) v th(off) r i f pwm t dead t int vamp(100%) vamp(200%) vamp(250%) vamp(0) oc t oc sc t sc uv d uv dr uv db uv dbr tdv t fo i fo(h) i fo(l) min. ma ma v v k w khz m s ns v v v mv a m s a m s v v v v m s ms m a ma typ. max. 0.8 2.5 1 2.2 1.5 3.0 5.0 4.3 11.0 11.5 10.1 10.6 1.0 1.4 3.0 50 100 2.0 4.0 50 5.3 10 8.0 2 12.0 12.5 10.8 11.3 10 1.8 50 5 2.0 4.0 15 2.5 5.0 100 8.0 13.0 13.5 11.6 12.1 1 15 unit electrical characteristics (tj = 25c, v d = 15v, v db = 15v unless otherwise noted) (note 3) : the dead-time has to be set externally by the cpu; it is not part of the asipm internal functions. (note 4) : fault output signaling is given only when the internal oc, sc, & uv protection circuits are activated. the oc, sc and uv protection (and fault output) operate for the lower arms only. the oc and sc protection fault output is given in a pulse format while that of uv protection is maintained throughout the duration of the under-voltage condition. condition symbol item ratings v cc v d v db d v d , v db v cin(on) v cin(off) t dead t c f pwm t xx supply voltage supply voltage supply voltage supply voltage ripple input on voltage input off voltage arm shoot-through blocking time module case operating temperature pwm input frequency allowable minimum input on-pulse width min. recommended operating conditions typ. max. 300 15.0 15.0 unit supply circuit under voltage protection 200 1 2 3 4 5 300 100 0 0 vamp (v) vamp (200%) vamp (100%) v d = 15v tj = 25? vamp actual load peak current (%), (i c = i o 5 2) (fig. 4) inverter dc-link igbt current analogue signaling output (typical)
mitsubishi semiconductor PS11032 flat-base type insulated type jan. 2000 sc ic(a) oc tw ( m s) over current trip level collector current short circuit trip level 10 2 0 current abnormality protective functions arm-shoot-through inter-lock protective function (fig. 7) protection is achieved by monitoring and filtering the n-side dc-bus current. the over-current protection is activated (after al- lowing a filtering time of 10 m s) when the line current reaches 250% of the rated load-current i o (rms). similarly, the short circuit protection is activated (after allowing a filtering time of 2 m s) when the line current reaches twice the rated collector-current (i c ). when a current trip-level is exceeded (oc or sc), all the n-side igbts are intercepted (turned off) and a fault-signal is output. after the fault-signal output duration (1.8 ms - typ.), the intercep- tion is reset at the following off input signal. however, since the fault may be repetitive, it is recommended to stop the system after the fault-signal is received and check the fault. the trip-level set- tings described above are summarized in the following figure: (fig. 5) p-side input signal : v cin(p) n-side input signal : v cin(n) on on p-side igbt gate : v ge(p) n-side igbt gate : v ge(n) a1 b4 b3 b2 b1 a4 a3 a2 0 0 (fig. 6) recommended i/o interface circuit description: (1) during the on-state of either of the upper-arm or the lower-arm igbt, the inter-lock protection circuit blocks any erroneous on pulses (re- sulting from input noise) from triggering the other arm igbt and thus it prevents the arm-shoot-through situation. (2) when two on-signals are received for both the upper and the lower arms, the signal received first will be passed to the igbt and the sec- ond signal will be blocked. the second signal will be passed to its corresponding igbt immediately after the first signal is of f. note: this protective function provides no fault signaling output. the dead-time has to be set using the micro-controller (cpu). b1. n-side normal on-signal t n-side igbt gate turns on. b2. simultaneous on-signals t p-side igbt gate remains off. b3. n-side receives off-signal t n-side igbt gate turns off. b4. immediately after (b3) t p-side igbt gate turns on. operation: a1. p-side normal on-signal t p-side igbt gate turns on. a2. n-side erroneous on-signal t n-side igbt gate remains off. a3. while p-side on-signal remains t p-side igbt gate remains on. a4. n-side normal on-signal t n-side igbt gate turns on. u p ,v p ,w p ,u n ,v n ,w n fo v(amp) gnd(logic) asipm 5v v d (15v) cpu r r 5.1k w 5v 10k w 0.1nf 0.1nf
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